The present invention relates generally to integrated circuits (IC) and methods of manufacturing integrated circuits. More particularly, the present invention relates to conductive lines and methods of forming conductive lines.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of vias (or pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
Conventional integrated circuits utilize vias to connect structures (e.g., gates, drain regions, source regions) and conductive lines. For example, a via can connect a gate above the substrate to a conductive line in a metal 1 layer; Vias can also interconnect conductive lines. For example, a via can connect a conductive line in a metal 1 layer to conductive line in a metal 2 layer. A via is typically a metal plug which extends through an insulative layer in a multilayer integrated circuit. Vias and barrier layers are discussed in U.S. Pat. Nos. 5,646,448; 5,770,519; and 5,639,691; each of which are assigned to the assignee of the present application.
A barrier layer is used to protect the via and insulative layer from metal diffusion and the via and conductive line from electromigration (EM). The barrier layer can contribute significantly to resistance associated with the via metal. Electromigration is the mass transport due to momentum exchange between conducting electrons and diffusing metal atoms. Electromigration causes progressive damage to the metal conductors in an integrated circuit. In general, metals are most susceptible to electromigration at very high current density and temperatures of 100xc2x0 C. or more.
Electromigration failures have been described by Stanley Wolf, Ph.D. in Silicon Processing for the VLSI Era, Lattice Press, Sunset Beach, California, Vol. 2, pp. 264-65 (1990). Dr. Wolf explains that a positive divergence of the motion of the ions of a conductor leads to an accumulation of vacancies, forming a void in the metal. Such voids may ultimately grow to a size that results in open-circuit failure of the conductive line.
Conventional conductive lines have utilized thin layers (e.g., approximately 4,000 Angstroms (xc3x85) thick) of aluminum or an alloy of aluminum. The conductive lines may also be fabricated with copper to reduce susceptibility to electromigration.
Other conventional conductive lines have utilized pure copper or copper alloy lines formed in a damascene process. According to a conventional damascene process, copper lines are filled by electroplating a trench in a dielectric layer. The dielectric layer is typically covered by a barrier and/or a seed layer before electroplating to fill the trench with copper. After the trench is filled with copper, a barrier layer is provided above a copper conductive line and a subsequent interlevel dielectric layer is provided.
Conventional metal lines or interconnect structures, especially copper line structures, can be subject to unconstrained void formation. Unconstrained void formation can be problematic throughout the conductive line, but is particularly problematic near vias and in longer conductive lines (e.g., lines having a length greater than a critical path length).
Unconstrained void formation is a mechanical and electrical phenomenon of electromigration. Unconstrained void formation occurs when a void forms and propagates through the line (i.e., holes grow in the molecular structure associated with the copper material). The voids can create open circuits that lead to integrated circuit device failure.
Thus, there is a need for a conductive line that is more resistant to unconstrained void formation. Further, there is a need for a method of forming a conductive line that is resistant to unconstrained void formation. Even further, there is a need for a copper line structure that utilizes barrier layer properties to reduce unconstrained void formation. Yet further, there is a need for a method of fabricating a copper line that utilizes barrier layer properties to reduce unconstrained void formation.
An exemplary embodiment is related to an integrated circuit. The integrated circuit includes at least one interconnect layer. The interconnect layer includes a number of conductive lines. Each of the conductive lines includes at least two pairs of a first layer containing copper and a second layer containing a barrier material.
According to another exemplary embodiment, the conductive lines can be disposed in a trench in a dielectric material. At least one of the conductive lines can extend into a second trench to form a conductive via. The pairs can have a V-shaped or U-shaped cross-sectional area at a point where the pair extends into the second trench.
Still another exemplary embodiment relates to a laminated conductive line for an interconnect layer of an integrated circuit. The laminated conductive line includes a first thin barrier layer above a bottom of a dielectric trench and a first thin copper layer above and in contact with the first thin barrier layer; The laminated conductive line can also include a second thin barrier layer above and in contact with the first thin copper layer and a second thin copper layer above and in contact with the second thin barrier layer.
Still yet another embodiment relates to a method of forming a laminated conductive line for an integrated circuit. The method includes providing a first barrier layer, providing a first copper layer, providing a second barrier metal layer, and providing a second copper layer.
Other principle features and advantages of the invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.